Computer Graphics & Design of 6 - bit 800 Msample / s DSDA A / D Converter for HDD Read Channel


The KIPS Transactions:PartA, Vol. 9, No. 1, pp. 93-98, Mar. 2002
10.3745/KIPSTA.2002.9.1.93,   PDF Download:

Abstract

This paper introduces the design of high-speed analog-to-digital converter (ADC) for hard disk drive (HDD) read channel applications. This circuit is based on fast regenerative autozero comparator for high speed and low-error rate comparison operation, and Double Speed Dual ADC (DSDA) architecture for efficiently increasing the overall conversion speed of ADC. A new type of thermometer-to-binary decoder appropriate for the autozero architecture is employed for no glitch decoding, simplifying the conventional structure significantly. This ADC is designed for 6-bit resolution, 800 Msample/s maximum conversion rate, 390 mW power dissipation, one clock cycle latency in 0.65 m CMOS technology.


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Cite this article
[IEEE Style]
K. M. Chung and D. Y. Chung, "Computer Graphics & Design of 6 - bit 800 Msample / s DSDA A / D Converter for HDD Read Channel," The KIPS Transactions:PartA, vol. 9, no. 1, pp. 93-98, 2002. DOI: 10.3745/KIPSTA.2002.9.1.93.

[ACM Style]
Kang Min Chung and Dai Young Chung. 2002. Computer Graphics & Design of 6 - bit 800 Msample / s DSDA A / D Converter for HDD Read Channel. The KIPS Transactions:PartA, 9, 1, (2002), 93-98. DOI: 10.3745/KIPSTA.2002.9.1.93.