Fault-Tolerant Design of Array Systems Using Multichip Modules


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 6, No. 12, pp. 3662-3674, Dec. 1999
10.3745/KIPSTE.1999.6.12.3662,   PDF Download:

Abstract

This paper addresses some design issues for establishing the optimal number of spare units in array systems manufactured using fault-tolerant multichip modules(MCM's) for massively parallel computing(MPC). We propose a new quantitative approach to an optimal cost-effective MCM system design under yield and reliability of fault-tolerant, MCM's. In particular, the issues of imperfect support circuitry, chip assembly yield and array topology are investigated. Extensive parametric results for the analysis are provided to show that our scheme can be applied to design arrays using MCM's for MPC applications more efficiently, subject to yield and reliability constraints.


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Cite this article
[IEEE Style]
S. S. Kim, "Fault-Tolerant Design of Array Systems Using Multichip Modules," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 6, no. 12, pp. 3662-3674, 1999. DOI: 10.3745/KIPSTE.1999.6.12.3662.

[ACM Style]
Sung Soo Kim. 1999. Fault-Tolerant Design of Array Systems Using Multichip Modules. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 6, 12, (1999), 3662-3674. DOI: 10.3745/KIPSTE.1999.6.12.3662.