Implementation of a LSB - First Digit - Serial Multiplier for Finite Fields GF ( 2m )


The KIPS Transactions:PartA, Vol. 9, No. 3, pp. 281-286, Sep. 2002
10.3745/KIPSTA.2002.9.3.281,   PDF Download:

Abstract

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication A(x)B(x) mod G(x) in finite fields GF(2^m). If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.


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Cite this article
[IEEE Style]
C. H. Kim, C. P. Hong, J. J. Woo, "Implementation of a LSB - First Digit - Serial Multiplier for Finite Fields GF ( 2m )," The KIPS Transactions:PartA, vol. 9, no. 3, pp. 281-286, 2002. DOI: 10.3745/KIPSTA.2002.9.3.281.

[ACM Style]
Chang Hoon Kim, Chun Pyo Hong, and Jong Jung Woo. 2002. Implementation of a LSB - First Digit - Serial Multiplier for Finite Fields GF ( 2m ). The KIPS Transactions:PartA, 9, 3, (2002), 281-286. DOI: 10.3745/KIPSTA.2002.9.3.281.