On Design for Elimination of the Merging Delay Time in the Multiple Vector Reduction ( Inner Product )


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 7, No. 12, pp. 3986-3994, Dec. 2000
10.3745/KIPSTE.2000.7.12.3986,   PDF Download:

Abstract

A multiple vector reductive processing occurs during the vector inner product operation ([C] = [A] . [B]) and proceeds at the hardware dyadic pipeline unit. Every scalar result has to be generated with the component merging delay time in the multiple vector reduction( ). In this paper we propose a new design method by which the component merging time could be eliminated from the multiple reduction and the scalar results from the reduction( ) could be generated nearly in the almost same condensed time as the input components are feeded in the dyadic pipeline unit( ) or the output components are drained out of the dyadic pipeline unit( ), so called a dedicated chained pipeline unit for only a inner product operation.


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Cite this article
[IEEE Style]
Y. I. Cho and H. R. Kweon, "On Design for Elimination of the Merging Delay Time in the Multiple Vector Reduction ( Inner Product )," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 7, no. 12, pp. 3986-3994, 2000. DOI: 10.3745/KIPSTE.2000.7.12.3986.

[ACM Style]
Young Il Cho and Hyeok Ryool Kweon. 2000. On Design for Elimination of the Merging Delay Time in the Multiple Vector Reduction ( Inner Product ). The Transactions of the Korea Information Processing Society (1994 ~ 2000), 7, 12, (2000), 3986-3994. DOI: 10.3745/KIPSTE.2000.7.12.3986.