Computer Graphics & A Generic BIST Builder of Multiple RAM Modules Embedded in ASIC Chips


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 5, No. 6, pp. 1633-1638, Jun. 1998
10.3745/KIPSTE.1998.5.6.1633,   PDF Download:

Abstract

In this paper we propose a generic BIST builder for the Embedded Multiple RAM module in ASICs. The BIST circuitry is automatically generated according to the specification of the target RAM Modules and the applying test algorithms to them. The BIST is designed using the TOP-DOWN technique and, thus, has the several advantages in the area of the selection of test algorithm, the development of the circuitry, and the reuse of the circuity. In addition, we have modified the existing serial interfacing approach to obtain smaller additional BIST circuitry and higher fault coverage and better BIST sharing of the target RAM Modules in ASICs.


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Cite this article
[IEEE Style]
C. J. Kwon, "Computer Graphics & A Generic BIST Builder of Multiple RAM Modules Embedded in ASIC Chips," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 5, no. 6, pp. 1633-1638, 1998. DOI: 10.3745/KIPSTE.1998.5.6.1633.

[ACM Style]
Chang Jong Kwon. 1998. Computer Graphics & A Generic BIST Builder of Multiple RAM Modules Embedded in ASIC Chips. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 5, 6, (1998), 1633-1638. DOI: 10.3745/KIPSTE.1998.5.6.1633.