A Predicate - Sensitive Scheduling Algorithm in Instruction - Level Parallelism Processors


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 5, No. 1, pp. 202-214, Jan. 1998
10.3745/KIPSTE.1998.5.1.202,   PDF Download:

Abstract

Exploitation of instruction-level parallelism(ILP) is an effective mechanism for improving the performance of modern super-scalar and VLIW processors. Various software techniques can be applied to increase ILP. Among these techniques, predicated execution is the one that increases the degree if ILP by allowing instruction from different basic blocks to be converted to a single basic block by removing branch instructions. In this paper, a global predicate-sensitive scheduling algorithm is proposed to improve the performance for ILP processors that support predicated execution. In order to examine the performance of proposed algorithm, a C compiler and a simulator are developed. By simulation various benchmark programs with the compiler and the simulators, the performance results of this algorithm are measured and the effectiveness of the algorithm is verified. As a result of measure performance with 1, 2, 4 issue execution, this study was confirmed average performance by 20% or more.


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Cite this article
[IEEE Style]
Y. B. Kang and L. S. Jeong, "A Predicate - Sensitive Scheduling Algorithm in Instruction - Level Parallelism Processors," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 5, no. 1, pp. 202-214, 1998. DOI: 10.3745/KIPSTE.1998.5.1.202.

[ACM Style]
Yoo Byung Kang and Lee Sang Jeong. 1998. A Predicate - Sensitive Scheduling Algorithm in Instruction - Level Parallelism Processors. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 5, 1, (1998), 202-214. DOI: 10.3745/KIPSTE.1998.5.1.202.