A Study on High Performance Floating Point Unit


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 4, No. 11, pp. 2861-2873, Nov. 1997
10.3745/KIPSTE.1997.4.11.2861,   PDF Download:

Abstract

An FPU(Floating Point Unit) is the principle component in high performance computer and is placed on a chip together with main processing unit recently. As a processing speed of the FPU is accelerated, the rounding stage, which occupies one of the floating point processing steps for floating point operations, has a considerable effect on overall floating point operations. In this paper, by studying and analyzing the processing flows of the conventional floating point adder/subtractor, multipler and divider, which are main component of the FPU, efficient rounding mechanisms are presented. Proposed mechanisms do not require any additional execution time and any high speed adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this approach.


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Cite this article
[IEEE Style]
P. W. Chan and H. T. Don, "A Study on High Performance Floating Point Unit," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 4, no. 11, pp. 2861-2873, 1997. DOI: 10.3745/KIPSTE.1997.4.11.2861.

[ACM Style]
Park Woo Chan and Han Tack Don. 1997. A Study on High Performance Floating Point Unit. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 4, 11, (1997), 2861-2873. DOI: 10.3745/KIPSTE.1997.4.11.2861.