Implementation of the Extended Data Encryption Standard (EDES)


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 4, No. 6, pp. 1565-1575, Jun. 1997
10.3745/KIPSTE.1997.4.6.1565,   PDF Download:

Abstract

A new encryption algorithm had been proposed as a replacement to the Data Encryption Standard (DES) in [1,2]. It called the Extended DES (EDES) has a key length of 112 bits. The plaintext data consists of 96 bits divided into 3 sub-blocks of 32 bits each. The EDES has a potentially higher resistance to differential cryptanalysis that the DES due to the asymmetric number of f functions performed on each of the 3 sub-blocks and due to the increase of S-boxes from 8 to 16.This paper propose a hardware design for the EDES and its implementation in VLSI. The VLSI chip implements data encryption and decryption in a single hardware unit. With a system clock frequency of 15Mhz the device permits a data conversion rate of about 90Mbit/sec. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols.


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Cite this article
[IEEE Style]
H. S. Jo, "Implementation of the Extended Data Encryption Standard (EDES)," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 4, no. 6, pp. 1565-1575, 1997. DOI: 10.3745/KIPSTE.1997.4.6.1565.

[ACM Style]
Han Seung Jo. 1997. Implementation of the Extended Data Encryption Standard (EDES). The Transactions of the Korea Information Processing Society (1994 ~ 2000), 4, 6, (1997), 1565-1575. DOI: 10.3745/KIPSTE.1997.4.6.1565.