A Study on the Development of a Tool for PLD Design


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 1, No. 3, pp. 391-397, Sep. 1994
10.3745/KIPSTE.1994.1.3.391,   PDF Download:

Abstract

In this paper, we have developed a PLD Designer which is a design tool for digital circuits design using PLD device. PLD designer consists of a state graphic editor to extract boolean equations from state table within 20 states of FSM and a pin map editor to assign pin map for PLD device(PAL16RA, PAL22V10, GAL16V8, etc), which is suitable for extracted boolean equations. Also pin map editor generates a necessary JEDEC file to implement PLD device by using fuse map and checksum algorithm. To verify extracted boolean equation, we have developed simulation test vector generation algorithm. The results of JEDEC files generated by PLD designer is same with the results of JEDEC files generated by PALASM.


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Cite this article
[IEEE Style]
K. H. Suk and W. C. Sang, "A Study on the Development of a Tool for PLD Design," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 1, no. 3, pp. 391-397, 1994. DOI: 10.3745/KIPSTE.1994.1.3.391.

[ACM Style]
Kim Hee Suk and Won Chung Sang. 1994. A Study on the Development of a Tool for PLD Design. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 1, 3, (1994), 391-397. DOI: 10.3745/KIPSTE.1994.1.3.391.