VLSI Architecture for High Speed Implementation of Elliptic Curve Cryptographic Systems


The KIPS Transactions:PartC, Vol. 15, No. 2, pp. 133-140, Apr. 2008
10.3745/KIPSTC.2008.15.2.133,   PDF Download:

Abstract

In this paper, we propose a high performance elliptic curve cryptographic processor over GF(2의 163제곱). The proposed architecture is based on a modified Lopez-Dahab elliptic curve point multiplication algorithm and uses Gaussian normal basis for  field arithmetic. To achieve a high throughput rates, we design two new word-level arithmetic units over and derive a parallelized elliptic curve point doubling and point addition algorithm with uniform addressing based on the Lopez-Dahab method. We implement our design using Xilinx XC4VLX80 FPGA device which uses 24,263 slices and has a maximum frequency of 143MHz. Our design is roughly 4.8 times faster with 2 times increased hardware complexity compared with the previous hardware implementation proposed by Shu. et. al. Therefore, the proposed elliptic curve cryptographic processor is well suited to elliptic curve cryptosystems requiring high throughput rates such as network processors and web servers.


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Cite this article
[IEEE Style]
C. H. Kim, "VLSI Architecture for High Speed Implementation of Elliptic Curve Cryptographic Systems," The KIPS Transactions:PartC, vol. 15, no. 2, pp. 133-140, 2008. DOI: 10.3745/KIPSTC.2008.15.2.133.

[ACM Style]
Chang Hoon Kim. 2008. VLSI Architecture for High Speed Implementation of Elliptic Curve Cryptographic Systems. The KIPS Transactions:PartC, 15, 2, (2008), 133-140. DOI: 10.3745/KIPSTC.2008.15.2.133.