Design of a 20 Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic


The KIPS Transactions:PartA, Vol. 15, No. 3, pp. 135-140, Jun. 2008
10.3745/KIPSTA.2008.15.3.135,   PDF Download:

Abstract

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC 0.18㎛standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.


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Cite this article
[IEEE Style]
J. B. Kim, "Design of a 20 Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic," The KIPS Transactions:PartA, vol. 15, no. 3, pp. 135-140, 2008. DOI: 10.3745/KIPSTA.2008.15.3.135.

[ACM Style]
Jeong Beom Kim. 2008. Design of a 20 Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic. The KIPS Transactions:PartA, 15, 3, (2008), 135-140. DOI: 10.3745/KIPSTA.2008.15.3.135.