Computer Graphics & Design of 1-D DCT processor using a new efficient computation sharing multiplier


The KIPS Transactions:PartA, Vol. 10, No. 4, pp. 347-356, Oct. 2003
10.3745/KIPSTA.2003.10.4.347,   PDF Download:

Abstract

The DCT algorithm needs efficient hardware architecture to compute inner product. The conventional methods have large hardware complexity. Because of this reason, a computation sharing multiplier was proposed for implementing inner product. However, the existing multiplier has inefficient hardware architecture in precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we proposed a new efficient computation sharing multiplier and applied it to implementation of 1-D DCT processor. The comparison results show that the new multiplier is more efficient than an old one when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using the proposed multiplier is more high performance than typical design methods.


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Cite this article
[IEEE Style]
L. T. Ug and J. S. Bog, "Computer Graphics & Design of 1-D DCT processor using a new efficient computation sharing multiplier," The KIPS Transactions:PartA, vol. 10, no. 4, pp. 347-356, 2003. DOI: 10.3745/KIPSTA.2003.10.4.347.

[ACM Style]
Lee Tae Ug and Jo Sang Bog. 2003. Computer Graphics & Design of 1-D DCT processor using a new efficient computation sharing multiplier. The KIPS Transactions:PartA, 10, 4, (2003), 347-356. DOI: 10.3745/KIPSTA.2003.10.4.347.