Computer Graphics & Design of Low Voltage 1.8V, Wide Range 50~500MHz Delay Locked Loop for DDR SDRAM


The KIPS Transactions:PartA, Vol. 10, No. 3, pp. 247-254, Aug. 2003
10.3745/KIPSTA.2003.10.3.247,   PDF Download:

Abstract

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 50MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.


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Cite this article
[IEEE Style]
G. I. Jae and J. G. Min, "Computer Graphics & Design of Low Voltage 1.8V, Wide Range 50~500MHz Delay Locked Loop for DDR SDRAM," The KIPS Transactions:PartA, vol. 10, no. 3, pp. 247-254, 2003. DOI: 10.3745/KIPSTA.2003.10.3.247.

[ACM Style]
Gu In Jae and Jeong Gang Min. 2003. Computer Graphics & Design of Low Voltage 1.8V, Wide Range 50~500MHz Delay Locked Loop for DDR SDRAM. The KIPS Transactions:PartA, 10, 3, (2003), 247-254. DOI: 10.3745/KIPSTA.2003.10.3.247.