Computer Graphics & Design of Low Voltage 1.8V, Wide Range 50~500MHz Delay Locked Loop for DDR SDRAM
The KIPS Transactions:PartA, Vol. 10, No. 3, pp. 247-254, Aug. 2003
10.3745/KIPSTA.2003.10.3.247, PDF Download:
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Cite this article
[IEEE Style]
G. I. Jae and J. G. Min, "Computer Graphics & Design of Low Voltage 1.8V, Wide Range 50~500MHz Delay Locked Loop for DDR SDRAM," The KIPS Transactions:PartA, vol. 10, no. 3, pp. 247-254, 2003. DOI: 10.3745/KIPSTA.2003.10.3.247.
[ACM Style]
Gu In Jae and Jeong Gang Min. 2003. Computer Graphics & Design of Low Voltage 1.8V, Wide Range 50~500MHz Delay Locked Loop for DDR SDRAM. The KIPS Transactions:PartA, 10, 3, (2003), 247-254. DOI: 10.3745/KIPSTA.2003.10.3.247.