Computer Graphics & A Study on Minimizing the Number of VDD/VSS Pins in Simultaneous Switching Environment


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 7, No. 7, pp. 2179-2187, Jul. 2000
10.3745/KIPSTE.2000.7.7.2179,   PDF Download:

Abstract

This paper provides a heuristic analysis technique which determines an optimal number of VDD/VSS pads meeting allowable Simultaneous Switching Noise(SSN) budget, early in the design phase. Until now, in determining the number of VDD/VSS pads, designers had to simulate packaging models case by case in the design phase or roughly allocate the power/ground pins in an inaccuate way according to typical design rules. However, due to the high density and frequency trends of IC technologies, the VDD/VSS pads allocation method can affect an adverse effect on IC operations, which requires more accurate and efficient methods be devised. Thus, this paper proposes an analytic VDD/VSS pads calculation method that gives a practical help for packaging designs early in the design phase. The proposed method is applied to a design example of a 1/8 × 208 pin plastic quad flat package(PQFP) and the results are verified through simulation using HSPICE.


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Cite this article
[IEEE Style]
Y. J. Bae, Y. O. Lee, J. H. Kim, B. G. Kim, "Computer Graphics & A Study on Minimizing the Number of VDD/VSS Pins in Simultaneous Switching Environment," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 7, no. 7, pp. 2179-2187, 2000. DOI: 10.3745/KIPSTE.2000.7.7.2179.

[ACM Style]
Yun Jeong Bae, Yun Ok Lee, Jae Ha Kim, and Byung Gi Kim. 2000. Computer Graphics & A Study on Minimizing the Number of VDD/VSS Pins in Simultaneous Switching Environment. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 7, 7, (2000), 2179-2187. DOI: 10.3745/KIPSTE.2000.7.7.2179.