Development of CPLD technology mapping algorithm for Sequential Circuit under Time Constraint
The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 7, No. 1, pp. 224-234, Jan. 2000
10.3745/KIPSTE.2000.7.1.224, PDF Download:
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Cite this article
[IEEE Style]
C. M. Youn and H. S. Kim, "Development of CPLD technology mapping algorithm for Sequential Circuit under Time Constraint," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 7, no. 1, pp. 224-234, 2000. DOI: 10.3745/KIPSTE.2000.7.1.224.
[ACM Style]
Chung Mo Youn and Hi Seok Kim. 2000. Development of CPLD technology mapping algorithm for Sequential Circuit under Time Constraint. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 7, 1, (2000), 224-234. DOI: 10.3745/KIPSTE.2000.7.1.224.