Sang Hoon Song

The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 7, No. 1, pp. 266-272, Jan. 2000
10.3745/KIPSTE.2000.7.1.266,   PDF Download:

Abstract

The square-based multiplication using look-up table simplifies the process and speeds-up the operating speed. However, the look-up table size increases exponentially as bit size increases. Recently, Wey and Shieh introduced a noble design of square generator circuit using a folding approach for high-speed performance applications. The design uses the ones complement values of ROM addresses to fold the huge look-up ROM table repeatedly such that a much smaller table can be sufficient to store the squares. We present new folding techniques that do not require a ones complement part, one of three major parts in the Wey and Shiehs method. Also the proposed techniques reduce the bit size of partial sums such that the hardware implementation be simplified and the performance be enhanced.

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