Computer Graphics & A Circuit Extractor Using Directional Edges for Design Verification of Integrated Circuit


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 5, No. 12, pp. 3244-3256, Dec. 1998
10.3745/KIPSTE.1998.5.12.3244,   PDF Download:

Abstract

Due to the high density of integration and the high performance in current integrated circuit, it is more emphasized to verify the electrical connectivity and performance of the circuit extracted from the layout. In this paper, we propose a new algorithm to extract the netlist including the geometric parameters of MOSFETs and the parasitic resistance and capacitance values. Where a set of polygon blocks for routing wires in the layout are described with directional edges and the layout extraction is carried out by checking over the abutment of these blocks on MOSFETs.


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Cite this article
[IEEE Style]
S. Y. Chan, P. S. Hong, Y. S. Dae, "Computer Graphics & A Circuit Extractor Using Directional Edges for Design Verification of Integrated Circuit," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 5, no. 12, pp. 3244-3256, 1998. DOI: 10.3745/KIPSTE.1998.5.12.3244.

[ACM Style]
Son Yeong Chan, Park Seog Hong, and Yu Sang Dae. 1998. Computer Graphics & A Circuit Extractor Using Directional Edges for Design Verification of Integrated Circuit. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 5, 12, (1998), 3244-3256. DOI: 10.3745/KIPSTE.1998.5.12.3244.