Computer Graphics & A Design of Space Compactor for low overhead in Built-In Self Test


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 5, No. 9, pp. 2378-2387, Sep. 1998
10.3745/KIPSTE.1998.5.9.2378,   PDF Download:

Abstract

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Under Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N-input logic gate and design the most efficient space response compactors according to the characteristics of output sequence from CUT. The proposed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated by LFSR(Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.


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Cite this article
[IEEE Style]
J. J. Mo, "Computer Graphics & A Design of Space Compactor for low overhead in Built-In Self Test," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 5, no. 9, pp. 2378-2387, 1998. DOI: 10.3745/KIPSTE.1998.5.9.2378.

[ACM Style]
Jung Jun Mo. 1998. Computer Graphics & A Design of Space Compactor for low overhead in Built-In Self Test. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 5, 9, (1998), 2378-2387. DOI: 10.3745/KIPSTE.1998.5.9.2378.