Dynamic Pattern Abstraction of a Logic Circuit Simulator and Its Speed Up


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 5, No. 8, pp. 2179-2189, Aug. 1998
10.3745/KIPSTE.1998.5.8.2179,   PDF Download:

Abstract

This paper presents the methodology to improve the computation efficiency of the simulation by developing the concept of the dynamic preservation and reutilization of the state transitions. The computation cost is enormous for the simulation of hardware described in hardware description languages including VHDL. Analyzing the process of simulation precisely, we have found that the number of the patterns for the state transition is limited if the sizes of hardware modules are determined properly. The patterns are preserved dynamically when they appeared first, and are utilized in later simulation in order to reduce the simulation costs. In this study, the efficiency of the present method was verified using case studies for the simulation.


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Cite this article
[IEEE Style]
L. P. Woo and K. Itano, "Dynamic Pattern Abstraction of a Logic Circuit Simulator and Its Speed Up," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 5, no. 8, pp. 2179-2189, 1998. DOI: 10.3745/KIPSTE.1998.5.8.2179.

[ACM Style]
Lee Phil Woo and Kozo Itano. 1998. Dynamic Pattern Abstraction of a Logic Circuit Simulator and Its Speed Up. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 5, 8, (1998), 2179-2189. DOI: 10.3745/KIPSTE.1998.5.8.2179.