A Perfomance Measurement and Evaluation System for ILP Processors


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 5, No. 8, pp. 2164-2178, Aug. 1998
10.3745/KIPSTE.1998.5.8.2164,   PDF Download:

Abstract

In this paper, a performance measurement and evaluation system for ILP(Instruction Level Parallelism) processors which issue multiple instructions and execute them in parallel is developed. The system consists of a C compiler and a simulator. The compiler takes C source programs as an input and generates 3-address style intermediate code. Then the simulator accepts the intermediate code and simulates it. The results of simulation are the contents of memory before and after simulation, the number of executed clocks, the trace and the dynamic count of executed instructions, the prediction hit ratio and profiling information for each branch instruction. To verify and understand the behavior of the system, the performance of predicated execution and one of branch schemes is measured and its results are analyzed.


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Cite this article
[IEEE Style]
L. S. Jeong, "A Perfomance Measurement and Evaluation System for ILP Processors," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 5, no. 8, pp. 2164-2178, 1998. DOI: 10.3745/KIPSTE.1998.5.8.2164.

[ACM Style]
Lee Sang Jeong. 1998. A Perfomance Measurement and Evaluation System for ILP Processors. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 5, 8, (1998), 2164-2178. DOI: 10.3745/KIPSTE.1998.5.8.2164.