Kang Min Sup

KIPS Transactions on Computer and Communication Systems, Vol. 8, No. 11, pp. 271-276, Nov. 2019
https://doi.org/10.3745/KTCCS.2019.8.11.271,   PDF Download:
Keywords: ARIA Crypto-Processor, Composite Field S-Box, Key scheduling, Verilog HDL
Abstract

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

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