Prediction-Based Parallel Gate-Level Timing Simulation Using Spatially Partial Simulation Strategy


KIPS Transactions on Computer and Communication Systems, Vol. 8, No. 3, pp. 57-64, Mar. 2019
https://doi.org/10.3745/KTCCS.2019.8.3.57, Full Text:
Keywords: Verification, Event-Driven Logic Simulation, Parallel Logic Simulation, Timing Simulation
Abstract

In this paper, an efficient prediction-based parallel simulation method using spatially partial simulation strategy is proposed for improving both the performance of the event-driven gate-level timing simulation and the debugging efficiency. The proposed method quickly generates the prediction data on-the-fly, but still accurately for the input values and output values of parallel event-driven local simulations by applying the strategy to the simulation at the higher abstraction level. For those six designs which had used for the performance evaluation of the proposed strategy, our method had shown about 3.7x improvement over the most general sequential event-driven gate-level timing simulation, 9.7x improvement over the commercial multi-core based parallel event-driven gate-level timing simulation, and 2.7x improvement over the best of previous prediction-based parallel simulation results, on average.


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Cite this article
[IEEE Style]
J. Han and S. Yang, "Prediction-Based Parallel Gate-Level Timing Simulation Using Spatially Partial Simulation Strategy," KIPS Transactions on Computer and Communication Systems, vol. 8, no. 3, pp. 57-64, 2019. DOI: https://doi.org/10.3745/KTCCS.2019.8.3.57.

[ACM Style]
Jaehoon Han and Seiyang Yang. 2019. Prediction-Based Parallel Gate-Level Timing Simulation Using Spatially Partial Simulation Strategy. KIPS Transactions on Computer and Communication Systems, 8, 3, (2019), 57-64. DOI: https://doi.org/10.3745/KTCCS.2019.8.3.57.