VLSI Design of a New Dynamic GSMP V3 Architecture


KIPS Transactions on Computer and Communication Systems, Vol. 8, No. 3, pp. 287-298, Jun. 2001
10.3745/KIPSTC.2001.8.3.287,   PDF Download:

Abstract

In this paper, the hardware architecture of Dynamic GSMP V3 (General Switch Management Protocol Version 3), an open interface protocol with resource management functions for efficient IP service on ATM over MPLS, is proposed and designed for VLSI implementation. And we compare and analyze the proposed GSMP with the GSMP under standardization process in terms of CLR (Cell Loss Rate). We design the Slave block of the Dynamic GSMP V3 using SAM-SUNG SoG 0.5 m process, which performs functions for switch connection control in the ATM Switch. In order to compare difference performanaces between the proposed method and the conventional one, we conducts simulations using the minimum buffer search algorithm with random cell generation. The exponential results show that the proposed method leads to performance enhancement in CLR.


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Cite this article
[IEEE Style]
Y. C. Kim, T. W. Lee, K. O. Kim and M. O. Lee, "VLSI Design of a New Dynamic GSMP V3 Architecture," KIPS Journal C (2001 ~ 2012) , vol. 8, no. 3, pp. 287-298, 2001. DOI: 10.3745/KIPSTC.2001.8.3.287.

[ACM Style]
Young Chul Kim, Tae Won Lee, Kwang Ok Kim, and Myung Ok Lee. 2001. VLSI Design of a New Dynamic GSMP V3 Architecture. KIPS Journal C (2001 ~ 2012) , 8, 3, (2001), 287-298. DOI: 10.3745/KIPSTC.2001.8.3.287.