Hardware Implementation of 128 - bit Cipher Algorithm Using FPGA


KIPS Transactions on Computer and Communication Systems, Vol. 8, No. 3, pp. 277-286, Jun. 2001
10.3745/KIPSTC.2001.8.3.277,   PDF Download:

Abstract

This paper implements two cipher algorithms, Rijndael and Twofish, with a hardware using the ALTERA FPGA. The former was selected as the AES (Advanced Encryption Standard) by NIST, and the latter was proven to have excellent stability and performance. Two algorithms are implemented in hardware with key scheduling and interface part. The size of the implemented circuit does not increase significantly even if it included the key scheduling for the efficient operation of algorithms. Thus, the throughput of encryption/decryption has been improved. The implemented Rijndael cipher algorithm has completed the key scheduling of a 128-bit symmetric key in 11 clocks, and Twofish algorithm in 21 clocks. Encryption/decryption has been performed in 10 clocks for Rijndael and in 16 clocks for Twofish with the same input data of 128-bit long. It is shown that the throughput of Rijndael is 336.8Mbps and that of Twofish is 121.2Mbps.


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Cite this article
[IEEE Style]
K. B. Lee and B. W. Lee, "Hardware Implementation of 128 - bit Cipher Algorithm Using FPGA," KIPS Journal C (2001 ~ 2012) , vol. 8, no. 3, pp. 277-286, 2001. DOI: 10.3745/KIPSTC.2001.8.3.277.

[ACM Style]
Keon Bae Lee and Byung Wook Lee. 2001. Hardware Implementation of 128 - bit Cipher Algorithm Using FPGA. KIPS Journal C (2001 ~ 2012) , 8, 3, (2001), 277-286. DOI: 10.3745/KIPSTC.2001.8.3.277.