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Search: "[ author: Seiyang Yang ]" (2)
Prediction-Based Parallel Gate-Level Timing Simulation Using Spatially Partial Simulation Strategy
Jaehoon Han, Seiyang Yang KIPS Transactions on Computer and Communication Systems,
Vol. 8, No. 3, pp. 57-64,
Mar.
2019
https://doi.org/10.3745/KTCCS.2019.8.3.57
Keywords: Verification, Event-Driven Logic Simulation, Parallel Logic Simulation, Timing Simulation
https://doi.org/10.3745/KTCCS.2019.8.3.57
Keywords: Verification, Event-Driven Logic Simulation, Parallel Logic Simulation, Timing Simulation
Performance Improvement of Prediction-Based Parallel Gate-Level Timing Simulation Using Prediction Accuracy Enhancement Strategy
Seiyang Yang KIPS Transactions on Computer and Communication Systems,
Vol. 5, No. 12, pp. 439-446,
Dec.
2016
10.3745/KTCCS.2016.5.12.439
Keywords: Verification, Event-Driven Logic Simulation, Parallel Logic Simulation
10.3745/KTCCS.2016.5.12.439
Keywords: Verification, Event-Driven Logic Simulation, Parallel Logic Simulation
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All publications of KTCCS is indexed in DOI, EBSCO, Google Scholar, Crossref, and CrossCheck.
KTCCS is also selected as the Journal for Accreditation by NRF (National Research Foundation of Korea).
