A Study of Delay Test for Sequential Circuit based on Boundary Scan Architecture
The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 5, No. 3, pp. 862-872, Mar. 1998
10.3745/KIPSTE.1998.5.3.862, PDF Download:
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Cite this article
[IEEE Style]
L. C. Hee, K. J. Hwan, Y. T. Jin, N. I. Gil, A. G. Seon, "A Study of Delay Test for Sequential Circuit based on Boundary Scan Architecture," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 5, no. 3, pp. 862-872, 1998. DOI: 10.3745/KIPSTE.1998.5.3.862.
[ACM Style]
Lee Chang Hee, Kim Jeong Hwan, Yun Tae Jin, Nam In Gil, and Ahn Gwang Seon. 1998. A Study of Delay Test for Sequential Circuit based on Boundary Scan Architecture. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 5, 3, (1998), 862-872. DOI: 10.3745/KIPSTE.1998.5.3.862.