A FPGA Implementation of BIST Design for the Batch Testing
The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 4, No. 7, pp. 1900-1906, Jul. 1997
10.3745/KIPSTE.1997.4.7.1900, PDF Download:
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Cite this article
[IEEE Style]
R. K. Hyeon, "A FPGA Implementation of BIST Design for the Batch Testing," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 4, no. 7, pp. 1900-1906, 1997. DOI: 10.3745/KIPSTE.1997.4.7.1900.
[ACM Style]
Rhee Kang Hyeon. 1997. A FPGA Implementation of BIST Design for the Batch Testing. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 4, 7, (1997), 1900-1906. DOI: 10.3745/KIPSTE.1997.4.7.1900.