Test Pattern Generation for Combinational Circuits using Inherited Values


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 4, No. 2, pp. 606-615, Feb. 1997
10.3745/KIPSTE.1997.4.2.606,   PDF Download:

Abstract

This paper proposes an efficient method for test pattern generation. Current test pattern generation systems generate a test vector for fault Fi 1 independently of the computation previously done for faults F1, F2, ..., Fi. The proposed algorithm generates a test vector for fault Fi 1 by inheriting the test vector for fault F1i. A new test vector is generated from inherited values by gradually changing the inherited values. The inherited values may partially activate a fault and propagate the fault signal. Normally, this reduces the number of decision steps and backtracks in the second search. Experimental results for well-known benchmark circuits show that the proposed algorithm is very efficient with small backtrack limit; in combination with other algorithms, it is very efficient for arbitrary backtrack limits.


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Cite this article
[IEEE Style]
S. S. Hoon, "Test Pattern Generation for Combinational Circuits using Inherited Values," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 4, no. 2, pp. 606-615, 1997. DOI: 10.3745/KIPSTE.1997.4.2.606.

[ACM Style]
Song Sang Hoon. 1997. Test Pattern Generation for Combinational Circuits using Inherited Values. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 4, 2, (1997), 606-615. DOI: 10.3745/KIPSTE.1997.4.2.606.