Design and Implementation of a Fault Simulation System for Mixed-level Combinational Logic Circuits


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 4, No. 1, pp. 311-323, Jan. 1997
10.3745/KIPSTE.1997.4.1.311,   PDF Download:

Abstract

This paper presents a fast fault simulation system for detecting stuck-at fault in mixed-level combinational logic circuits with gate level and switch-level primitives. For a practical fault simulator, the circuit types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well-known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.


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Cite this article
[IEEE Style]
P. Y. Ho, S. J. Woo, P. E. Sei, "Design and Implementation of a Fault Simulation System for Mixed-level Combinational Logic Circuits," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 4, no. 1, pp. 311-323, 1997. DOI: 10.3745/KIPSTE.1997.4.1.311.

[ACM Style]
Park Young Ho, Sohn Jin Woo, and Park Eun Sei. 1997. Design and Implementation of a Fault Simulation System for Mixed-level Combinational Logic Circuits. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 4, 1, (1997), 311-323. DOI: 10.3745/KIPSTE.1997.4.1.311.