An Extended Scan Path Architecture Based on IEEE 1149.1


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 3, No. 7, pp. 1924-1937, Dec. 1996
10.3745/KIPSTE.1996.3.7.1924,   PDF Download:

Abstract

In this paper, we propose a ESP(Extended Scan Path) architecture for multi-board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there ar additional singles in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan path is either short or open, it doesn''t affect remaining other scan paths. as a result of executing parallel BIST and IEEE 1149.1 boundary scan path architecture. Because the ESP architecture uses the common bus, there are not additional signals in multi-board testing. By comparing the ESP architecture with conventional one using ISCAS''85 benchmark circuit, we showed that the architecture has improved results.


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Cite this article
[IEEE Style]
S. W. Jung, Y. T. Jin, A. G. Seon, "An Extended Scan Path Architecture Based on IEEE 1149.1," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 3, no. 7, pp. 1924-1937, 1996. DOI: 10.3745/KIPSTE.1996.3.7.1924.

[ACM Style]
Son Woo Jung, Yun Tai Jin, and Ahn Gwang Seon. 1996. An Extended Scan Path Architecture Based on IEEE 1149.1. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 3, 7, (1996), 1924-1937. DOI: 10.3745/KIPSTE.1996.3.7.1924.