Chang June Young, Lee Guee Sang

The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 3, No. 3, pp. 640-654, Apr. 1996
10.3745/KIPSTE.1996.3.3.640,   PDF Download:

Abstract

This paper presents a synthesis method for multy-level Reed-Muller circuits using BDDs(Binary Decision Diagrams). The existing synthesis tool for Reed-Muller circuits, FACTOR, is not appropriate to the synthesis of large circuits because it uses matrix(map-type) to represent given logic functions, resuleing in the exponential time and space in number of input to the circuits. For solving this problems, a synthesis method based on BDD is presented. Using BDDs, logic functions are represented compactly. Therefore storage spaces and computing time for synthesizing logic funtions were greatly decreased, and this technique can be easily applied to large circuits. Using BDD representaltons, the proposed method extract best patterns to minimize multi-level corcuits. Therefore resulting circuits are with AND/XOR gate which form a unique class of multi-level Reed-Muller circuits with good performance in area optimization and testavility. Experimental results using the proposed method show better performance than those using previous method[2]. for large circuits of considering the best input partition, synthesis results have been improved.

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