Test Generation for Partial Scanned Sequential Circuits Based on Boolean Function Manipulation


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 3, No. 3, pp. 572-580, Apr. 1996
10.3745/KIPSTE.1996.3.3.572,   PDF Download:

Abstract

This paper describes a test generation method for sequential circuits which improves the application limits of the IPMT method by applying the partial scan design to the IPMT method. To solve the problem that the IPMT method requires enormous computation time in image computation, and generates test patterns after the partial scan design is introdused to reduce test complexity. Scan flip-flops are selected for the partial scan design according to the node seze of the state functions of a sequential cicuit in their binary decision diagram representaltions. Experimental results on ISCAS''95 benchmark circuits show that a test generator based on our method has achieved 100% fault coverage by use of either 20% scan FFs for s344, s349, and s420 0r 80% scan FFs for s1423. However, test generators based on the previous IPMT method have not achieived 100% fault coverage for those circuits.


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Cite this article
[IEEE Style]
C. H. Yong, "Test Generation for Partial Scanned Sequential Circuits Based on Boolean Function Manipulation," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 3, no. 3, pp. 572-580, 1996. DOI: 10.3745/KIPSTE.1996.3.3.572.

[ACM Style]
Choi Ho Yong. 1996. Test Generation for Partial Scanned Sequential Circuits Based on Boolean Function Manipulation. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 3, 3, (1996), 572-580. DOI: 10.3745/KIPSTE.1996.3.3.572.