Technology Mapping of Sequential Logic for TLU-Type FPGAs


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 3, No. 3, pp. 564-571, Apr. 1996
10.3745/KIPSTE.1996.3.3.564,   PDF Download:

Abstract

The logic synthesis for table look up(TLU) type field programmable gate arrays(FPGAs) have so far studied mostly the combinationnal logic problem. This paper presents for mapping a sequential circuit onto a popular table look up architecturem the Zilinx 3090 architecture. In the first for solving this problem, combinational and sequential elements which have 6 or 7 input combinational and sequential elements are mapped onto two-output CLBs using sequential mergeability conditions. Finally we assigned the combinational and sequential elements which have less than or equal to 5 inputs. We heavily use the combinational synthesis techniques to solve the sequential systhesis problem. Our synthesis approach is very simple, but its results are reasonable. We compare several benchmark examples with sis-pga(map_together and map_separate) synthesis system and the experimental results show that our synthesis system is 17% better than sis-pga sequential synthesis system for TLU PGAs.


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Cite this article
[IEEE Style]
P. J. Hyun and K. B. Gwan, "Technology Mapping of Sequential Logic for TLU-Type FPGAs," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 3, no. 3, pp. 564-571, 1996. DOI: 10.3745/KIPSTE.1996.3.3.564.

[ACM Style]
Park Jang Hyun and Kim Bo Gwan. 1996. Technology Mapping of Sequential Logic for TLU-Type FPGAs. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 3, 3, (1996), 564-571. DOI: 10.3745/KIPSTE.1996.3.3.564.