A Study on the Design of Parallel Multiplier Array for the Multiplication Speed Up
The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 2, No. 6, pp. 969-973, Nov. 1995
10.3745/KIPSTE.1995.2.6.969, PDF Download:
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[IEEE Style]
R. K. Hyeon, "A Study on the Design of Parallel Multiplier Array for the Multiplication Speed Up," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 2, no. 6, pp. 969-973, 1995. DOI: 10.3745/KIPSTE.1995.2.6.969.
[ACM Style]
Rhee Kang Hyeon. 1995. A Study on the Design of Parallel Multiplier Array for the Multiplication Speed Up. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 2, 6, (1995), 969-973. DOI: 10.3745/KIPSTE.1995.2.6.969.