On a Design and Implementation Technique of a Universal ATPG for VLSI Circuits


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 2, No. 3, pp. 425-432, Apr. 1995
10.3745/KIPSTE.1995.2.3.425,   PDF Download:

Abstract

In this paper we propose a design and implementation technique of a universal automatic test pattern generator(UATPG) which is well suited for VLSI digital circuits. UATPG is designed to extend the capabilities of the existing ATPG and to provide a convenient environment to computer-aided design(CAD) users. We employ heuristic techniques in line justification and fault propagation for functional gates during test pattern generation for a target fault. In additions, this flip-flops associated with design for testability(DFT) are exploited for pseudo PIs and pseudo POs to enhance the testabilities of VLSI circuits. As a result, UATPG shows a good enhancement in convenient usage and performance.


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Cite this article
[IEEE Style]
C. J. Kwon, "On a Design and Implementation Technique of a Universal ATPG for VLSI Circuits," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 2, no. 3, pp. 425-432, 1995. DOI: 10.3745/KIPSTE.1995.2.3.425.

[ACM Style]
Chang Jong Kwon. 1995. On a Design and Implementation Technique of a Universal ATPG for VLSI Circuits. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 2, 3, (1995), 425-432. DOI: 10.3745/KIPSTE.1995.2.3.425.