A Design of CMOS Analog-Digital Converter for High-Speed Low-power Applications


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 2, No. 1, pp. 66-74, Jan. 1995
10.3745/KIPSTE.1995.2.1.66,   PDF Download:

Abstract

A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at 5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high-speed, low-power consumption, small area applications and one-chip mixed Analog-Digital system. Simulations are performed with PSPICE and a fabricated chip is tested.


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Cite this article
[IEEE Style]
Y. S. Dae, H. K. Tae, C. K. Min, "A Design of CMOS Analog-Digital Converter for High-Speed Low-power Applications," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 2, no. 1, pp. 66-74, 1995. DOI: 10.3745/KIPSTE.1995.2.1.66.

[ACM Style]
Yi Seong Dae, Hong Kuk Tae, and Chung Kang Min. 1995. A Design of CMOS Analog-Digital Converter for High-Speed Low-power Applications. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 2, 1, (1995), 66-74. DOI: 10.3745/KIPSTE.1995.2.1.66.