A Cache-based Reconfigurable Accelerator in Die-stacked DRAM


KIPS Transactions on Computer and Communication Systems, Vol. 4, No. 2, pp. 41-46, Feb. 2015
10.3745/KTCCS.2015.4.2.41,   PDF Download:

Abstract

The demand on low power and high performance system is soaring due to the extending of mobile and small electronic device market. The 3D die-stacking technology is widely studying for next generation integration technology due to its high density and low access time. We proposed the 3D die-stacked DRAM including a reconfigurable accelerator in a logic layer of DRAM. Also we discuss and suggest a cache-based local memory for a reconfigurable accelerator in a logic layer. The reconfigurable accelerator in logic layer of 3D die-stacked DRAM reduces the overhead of data management and transfer due to the characteristics of its location, so that can increase the performance highly. The proposed system archives 24.8 speedup in maximum.


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Cite this article
[IEEE Style]
Y. J. Kim, "A Cache-based Reconfigurable Accelerator in Die-stacked DRAM," KIPS Transactions on Computer and Communication Systems, vol. 4, no. 2, pp. 41-46, 2015. DOI: 10.3745/KTCCS.2015.4.2.41.

[ACM Style]
Yong Joo Kim. 2015. A Cache-based Reconfigurable Accelerator in Die-stacked DRAM. KIPS Transactions on Computer and Communication Systems, 4, 2, (2015), 41-46. DOI: 10.3745/KTCCS.2015.4.2.41.