Design and Evaluation of 32-Bit RISC-V Processor Using FPGA


KIPS Transactions on Computer and Communication Systems, Vol. 11, No. 1, pp. 1-8, Jan. 2022
https://doi.org/10.3745/KTCCS.2022.11.1.1,   PDF Download:  
Keywords: RISC-V, FPGA, Processor
Abstract

RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension.


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Cite this article
[IEEE Style]
S. Jang, S. Park, G. Kwon, T. Suh, "Design and Evaluation of 32-Bit RISC-V Processor Using FPGA," KIPS Transactions on Computer and Communication Systems, vol. 11, no. 1, pp. 1-8, 2022. DOI: https://doi.org/10.3745/KTCCS.2022.11.1.1.

[ACM Style]
Sungyeong Jang, Sangwoo Park, Guyun Kwon, and Taeweon Suh. 2022. Design and Evaluation of 32-Bit RISC-V Processor Using FPGA. KIPS Transactions on Computer and Communication Systems, 11, 1, (2022), 1-8. DOI: https://doi.org/10.3745/KTCCS.2022.11.1.1.