Prediction-Based Parallel Gate-Level Timing Simulation Using Spatially Partial Simulation Strategy
KIPS Transactions on Computer and Communication Systems, Vol. 8, No. 3, pp. 57-64, Mar. 2019
https://doi.org/10.3745/KTCCS.2019.8.3.57, PDF Download:
Keywords: Verification, Event-Driven Logic Simulation, Parallel Logic Simulation, Timing Simulation
Abstract
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Cite this article
[IEEE Style]
J. Han and S. Yang, "Prediction-Based Parallel Gate-Level Timing Simulation Using Spatially Partial Simulation Strategy," KIPS Transactions on Computer and Communication Systems, vol. 8, no. 3, pp. 57-64, 2019. DOI: https://doi.org/10.3745/KTCCS.2019.8.3.57.
[ACM Style]
Jaehoon Han and Seiyang Yang. 2019. Prediction-Based Parallel Gate-Level Timing Simulation Using Spatially Partial Simulation Strategy. KIPS Transactions on Computer and Communication Systems, 8, 3, (2019), 57-64. DOI: https://doi.org/10.3745/KTCCS.2019.8.3.57.