On a Logical Path Design for Optimizing Power-delay under a Fixed-delay Constraint


The KIPS Transactions:PartA, Vol. 17, No. 1, pp. 27-32, Feb. 2010
10.3745/KIPSTA.2010.17.1.27,   PDF Download:

Abstract

Logical Effort is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. In this paper, we propose an equal delay model and, based on this, a method of optimizing power-delay efficiency in a logical path. We simulate three designs of an eight-input AND gate using our technique. Our results show about 40% greater efficiency in power dissipation than those of Logical Effort method.


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Cite this article
[IEEE Style]
S. H. Lee and J. K. Chang, "On a Logical Path Design for Optimizing Power-delay under a Fixed-delay Constraint," The KIPS Transactions:PartA, vol. 17, no. 1, pp. 27-32, 2010. DOI: 10.3745/KIPSTA.2010.17.1.27.

[ACM Style]
Seung Ho Lee and Jong Kwon Chang. 2010. On a Logical Path Design for Optimizing Power-delay under a Fixed-delay Constraint. The KIPS Transactions:PartA, 17, 1, (2010), 27-32. DOI: 10.3745/KIPSTA.2010.17.1.27.