Low-power Data Cache using Selective Way Precharge


The KIPS Transactions:PartA, Vol. 16, No. 1, pp. 27-34, Feb. 2009
10.3745/KIPSTA.2009.16.1.27,   PDF Download:

Abstract

Recently, power saving with high performance is one of the hot issues in the mobile systems. Various technologies are introduced to achieve low-power processors, which include sub-micron semiconductor fabrication, voltage scaling, speed scaling and etc. In this paper, we introduce a new method that reduces of energy loss at the data cache. Our methods take the benefits in terms of speed and energy loss using selective way precharging of way prediction with concurrent way selecting. By the simulation results, our method achieves 10.2% energy saving compared to the way prediction method, and 56.4% energy saving compared to the common data cache structure.


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Cite this article
[IEEE Style]
B. C. Choi and H. J. Suh, "Low-power Data Cache using Selective Way Precharge," The KIPS Transactions:PartA, vol. 16, no. 1, pp. 27-34, 2009. DOI: 10.3745/KIPSTA.2009.16.1.27.

[ACM Style]
Byeong Chang Choi and Hyo Joong Suh. 2009. Low-power Data Cache using Selective Way Precharge. The KIPS Transactions:PartA, 16, 1, (2009), 27-34. DOI: 10.3745/KIPSTA.2009.16.1.27.