An Energy Efficient and High Performance Data Cache Structure Utilizing Tag History of Cache Addresses


The KIPS Transactions:PartA, Vol. 14, No. 1, pp. 55-62, Feb. 2007
10.3745/KIPSTA.2007.14.1.55,   PDF Download:

Abstract

Uptime of embedded processors for mobile devices are dependent on battery consumption. Especially the large portion of power consumption is known to be due to cache management in embedded processors. This paper proposes an energy efficient data cache structure for high performance embedded processors. High performance prefetching data cache issues prefetching instructions before issuing demand-fetch instructions based on reference predictions. These prefetching instructions bring reduction on memory delay by improving cache hit ratio, but on the other hand those increase energy consumption in proportion to the number of prefetching instructions. In this paper, we adopt tag history table on prefetching data cache for reducing energy consumption by minimizing parallel tag comparison. Experimental results show the proposed data cache improves performance on energy consumption as well as memory delay.


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Cite this article
[IEEE Style]
H. J. Moon and S. H. Jee, "An Energy Efficient and High Performance Data Cache Structure Utilizing Tag History of Cache Addresses," The KIPS Transactions:PartA, vol. 14, no. 1, pp. 55-62, 2007. DOI: 10.3745/KIPSTA.2007.14.1.55.

[ACM Style]
Hyun Ju Moon and Sung Hyun Jee. 2007. An Energy Efficient and High Performance Data Cache Structure Utilizing Tag History of Cache Addresses. The KIPS Transactions:PartA, 14, 1, (2007), 55-62. DOI: 10.3745/KIPSTA.2007.14.1.55.