Computer Graphics & The Design and Implementation of Outer Encoder/Decoder for Terrestrial DMB


The KIPS Transactions:PartA, Vol. 11, No. 1, pp. 81-88, Feb. 2004
10.3745/KIPSTA.2004.11.1.81,   PDF Download:

Abstract

In this paper, we designed the ourter encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes(16bytes) from the input packet(188byte) of MPEG-2 TS and the encoded data was distrivuted output by the convolutional interleaver for preventing burst errors. In the decoder part, it was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8bytes in packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.


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Cite this article
[IEEE Style]
W. J. Yeon, L. J. Hong, K. Geon, "Computer Graphics & The Design and Implementation of Outer Encoder/Decoder for Terrestrial DMB," The KIPS Transactions:PartA, vol. 11, no. 1, pp. 81-88, 2004. DOI: 10.3745/KIPSTA.2004.11.1.81.

[ACM Style]
Won Ji Yeon, Lee Jae Hong, and Kim Geon. 2004. Computer Graphics & The Design and Implementation of Outer Encoder/Decoder for Terrestrial DMB. The KIPS Transactions:PartA, 11, 1, (2004), 81-88. DOI: 10.3745/KIPSTA.2004.11.1.81.