Seo Hyo Jung

The KIPS Transactions:PartA, Vol. 11, No. 1, pp. 49-56, Feb. 2004
10.3745/KIPSTA.2004.11.1.49,   PDF Download:

Abstract

The performance of the multiprocessor system is limited by the several factors. The system performance is affected by the processor speed, memory delay, and interconnection network bandwidth/latency. By the evolution f semiconductor technology, off the shelf microprocessor speed breaks beyond GHz, and the processors can be scalable up to multiprocessor system by connecting through the interconnection networks. In this situation, the system performances are bound by the latencies and the bandwidth of the interconnection networks. SCI, Myrinet, and Gigabit Ethernet are widely adopted as a high-speed interconnection network links for the high performance cluster systems. Performance improvement of the interconnection network can be achieved by the bandwidth extension and the latency minimization. Speed up of the operation clock speed is asimple way to accomplish the bandwidth and latency betterment, while its physical distance makes the difficulties to attain the high interconnection network is one of the solutions to resolve the bottleneck of the scalable systems. Dual-ring SCI link structure is an example of the interconnection network improvement,. In this paper, I propose a network topology and a transaction path algorism, which optimize the latency and the efficiency under the duplicated links. By the simulation results, the proposed structure shiws 1.05 to 1.11 times better latency, and exhibit 1.42 to 2.1 times faster execution compared to the dual ring system.

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