Computer Graphics & New High Speed Parallel Multiplier for Real Time Multimedia Systems


The KIPS Transactions:PartA, Vol. 10, No. 6, pp. 671-676, Dec. 2003
10.3745/KIPSTA.2003.10.6.671,   PDF Download:

Abstract

In this paper, we proposed a new First Partial product Addition (FPA) architecture with new compressor (or parallel counter) to CSA tree built in the process of adding partial product for improving speed in the fast parallel multiplier to improve the speed of calculating partial product by about 20% compared with existing parallel counter using full Adder. The new circuit reduces the CLA bit finding final sum by N/2 using the novel FPA architecture. A 5.14nS of multiplication speed of the 16×16 multiplier is obtained using 0.25um CMOS technology. The architecture of the multiplier is easily opted for pipeline design and demonstrates high speed performance.


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Cite this article
[IEEE Style]
J. B. Log and L. M. Og, "Computer Graphics & New High Speed Parallel Multiplier for Real Time Multimedia Systems," The KIPS Transactions:PartA, vol. 10, no. 6, pp. 671-676, 2003. DOI: 10.3745/KIPSTA.2003.10.6.671.

[ACM Style]
Jo Byeong Log and Lee Myeong Og. 2003. Computer Graphics & New High Speed Parallel Multiplier for Real Time Multimedia Systems. The KIPS Transactions:PartA, 10, 6, (2003), 671-676. DOI: 10.3745/KIPSTA.2003.10.6.671.