Performance Improvement Through Aggressive Instruction Packing


The KIPS Transactions:PartA, Vol. 9, No. 2, pp. 231-240, Jun. 2002
10.3745/KIPSTA.2002.9.2.231,   PDF Download:

Abstract

This paper proposes balancing scheduling effort more evenly between the compiler and the processor, by introducing independently scheduled VLIW instructions. Aggressively Packed VLIW (APVLIW) processor is aimed specifically at independent scheduling Very Long Instruction Word (VLIW) instructions with dependency information. The APVLIW processor independently schedules each instruction within long instructions using functional unit and dynamic scheduler pairs. Every dynamic scheduler dynamically checks for data dependencies and resource collisions while scheduling each instruction. This scheduling is especially effective in applications containing loops. We simulate the architecture and show that the APVLIW processor performs significantly better than the VLIW processor for a wide range of cache sizes and across various numerical benchmark applications.


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Cite this article
[IEEE Style]
S. H. Jee and S. K. Kim, "Performance Improvement Through Aggressive Instruction Packing," The KIPS Transactions:PartA, vol. 9, no. 2, pp. 231-240, 2002. DOI: 10.3745/KIPSTA.2002.9.2.231.

[ACM Style]
Sung Hyun Jee and Su Kil Kim. 2002. Performance Improvement Through Aggressive Instruction Packing. The KIPS Transactions:PartA, 9, 2, (2002), 231-240. DOI: 10.3745/KIPSTA.2002.9.2.231.