Sung Kyo Choi, Kyung San Cho

The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 7, No. 7, pp. 2196-2203, Jul. 2000
10.3745/KIPSTE.2000.7.7.2196,   PDF Download:

Abstract

As processor's operational frequency increases and processors execute multiple instructions per cycle, the processor performance becomes more dependent on the load operand referencing latency and the data dependency. To reduce the operand fetch latency and to increase ILP by breaking the data dependency, we propose a value-address hybrid predictor using a reasonable sized prediction buffer and analyse the performance improvement by the proposed predictor. Through the extensive simulation of 5 benchmark programs, the proposed hybrid prediction scheme accurately predicts 62.72% of all loads which are 12.64% higher than the value prediction scheme and shows its cost-effectiveness compared to the address prediction scheme. In addition, we analyse the performance improvement achieved by the stride management and the history of previous predictions.

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