A Hardware Allocation and Binding Algorithm for ASIC Design


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 7, No. 4, pp. 1255-1262, Apr. 2000
10.3745/KIPSTE.2000.7.4.1255,   PDF Download:

Abstract

This paper proposes a hardware allocation and binding algorithm for ASIC Design. The proposed algorithm works on schedules input graph and simultaneously allocates and binds functional units, interconnections and registers by considering interdependency between operations and storage elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. Especially, he register allocation is executes the allocation optimal using graph coloring. This paper shows the effectiveness of the algorithm by comparing experiments to determine number of functional unit and register in advance or to separate executing allocation and binding of existing system.


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Cite this article
[IEEE Style]
J. Y. Cho, C. H. Lin, H. S. Kim, "A Hardware Allocation and Binding Algorithm for ASIC Design," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 7, no. 4, pp. 1255-1262, 2000. DOI: 10.3745/KIPSTE.2000.7.4.1255.

[ACM Style]
Ji Young Cho, Chi Ho Lin, and Hi Seok Kim. 2000. A Hardware Allocation and Binding Algorithm for ASIC Design. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 7, 4, (2000), 1255-1262. DOI: 10.3745/KIPSTE.2000.7.4.1255.