Design and Implementation of a Fault Simulation System for Mixed-level Combinational Logic Circuits
The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 4, No. 1, pp. 311-323, Jan. 1997
10.3745/KIPSTE.1997.4.1.311, PDF Download:
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Cite this article
[IEEE Style]
P. Y. Ho, S. J. Woo, P. E. Sei, "Design and Implementation of a Fault Simulation System for Mixed-level Combinational Logic Circuits," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 4, no. 1, pp. 311-323, 1997. DOI: 10.3745/KIPSTE.1997.4.1.311.
[ACM Style]
Park Young Ho, Sohn Jin Woo, and Park Eun Sei. 1997. Design and Implementation of a Fault Simulation System for Mixed-level Combinational Logic Circuits. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 4, 1, (1997), 311-323. DOI: 10.3745/KIPSTE.1997.4.1.311.