Design of Iterative Divider in GF(2(163)) Based on Improved Binary Extended GCD Algorithm


The KIPS Transactions:PartC, Vol. 17, No. 2, pp. 145-152, Apr. 2010
10.3745/KIPSTC.2010.17.2.145,   PDF Download:

Abstract

In this paper, we first propose a fast division algorithm in GF(2163) using standard basis representation, and then it is mapped into divider for GF(2163) with iterative hardware structure. The proposed algorithm is based on the binary ExtendedGCD algorithm, and the arithmetic operations for modular reduction are performed within only one “while-statement” unlike conventional approach which uses two “while-statement”. In this paper, we use reduction polynomial f(x)=x163 x7 x6 x3 1 that is recommended in SEC2(Standards for Efficient Cryptography) using standard basis representation, where degree m = 163. We also have implemented the proposed iterative architecture in FPGA using Verilog HDL, and it operates at a clock frequency of 85 MHz on Xilinx-VirtexII XC2V8000 FPGA device. From implementation results, we will show that computation speed of the proposed scheme is significantly improved than the existing two approaches.


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Cite this article
[IEEE Style]
M. S. Kang and B. C. Jeon, "Design of Iterative Divider in GF(2(163)) Based on Improved Binary Extended GCD Algorithm," The KIPS Transactions:PartC, vol. 17, no. 2, pp. 145-152, 2010. DOI: 10.3745/KIPSTC.2010.17.2.145.

[ACM Style]
Min Sup Kang and Byong Chan Jeon. 2010. Design of Iterative Divider in GF(2(163)) Based on Improved Binary Extended GCD Algorithm. The KIPS Transactions:PartC, 17, 2, (2010), 145-152. DOI: 10.3745/KIPSTC.2010.17.2.145.